Self-Configuration of Defective Cellular Arrays

Rapid adv an ces in VLSI technology are making it feasible to cons ider th e const ruction of parallel compute rs with very lar ge numbers of cells. On e promising architecture for such computers is a VLSI cellula r array that interconnects many simp le processing cells on a single lar ge chip or wafer. It will be very difficult , however, to make a chip of this kind without many defects. With a fixed int erconn ection pattern between cells, the whole cellular array may not he usable when there are any defects. Furthermore , an architecture with a fixed interconnection pattern is limited in the range of computations t hat can support efficiently. By providing reconfiguration mechanisms, a VLSI cellular array can be des igned so t hat it can be reconfig ured for fau lt-tolerance and specialized for var ious computations. This paper di scusses a massively fault -tolerant cellular array, wh ich contains ident ical cells with connections on ly to immediate nei ghb ors, where the cells and the connections may be de fective with a high probability. The cell can function as a processin g element, as a memory, or as a switchin g element that connects to ot her cells. On t he defect ive array, a large clus ter of interconnected working cells is formed , and the working cells in t he cluster are configured into a gra ph th at de termines the function of the ar ray. The de tailed architecture of the massively faul ttolerant cellular array is described, and the distributed algorithms for forming the cluster of working cells and configuring the cells into a linear array, a two-dimension al array, a binary t ree, and signal How gr aphs for various filters are prese nted. Simulation data are presented when bo th cells an d con nec t ions are de fect ive with various probabilit ies.